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MultiPig+ Kit
The MultiPig + Kit

MultiPig+ CW Transceiver Kit Construction

Introduction

The kit is neatly packed in a number of paper bags one for each module

PhaseLockLoop Kit
FreqCounterController Kit
Receiver Kit
Low Pass Filter Kit
Band Pass Filter Kit
Transmitter Kit
SWR/Power Meter Kit

 

29th Jan - The Freq Counter Controller Kit

The board is somehow smaller than I imagined, The resistors required very careful checking. tested IF offset all OK but the frequency counter just showed 0hz.. Frustrating, just don't seem to have a lot of luck with counters..

Took a break to get to grips with the Scope, and after a run through with Tom, tracing the various signals through the minicounter, I had a better idea of how to use the scope.

MultiPig FCC
FCC

Having listened to Winston and sampled an Old Empire (As no Scotch and Soda was to hand). I was inspired to work through the FCC and resolve the problem. Circuit diagram in one hand and scope probe in the other I followed the signal path from the VCO to the 4060 (With much switching of scope controls, on the way) on the input a nice squarewave is observed... Ah and onto the output pin of the 4060.. an identical squarewave.. Checking further, the input and ouput pins aren't soldered into the board, so are floating all by themselves! I had been using so little solder, that I did not noticed these pins had none! Soldered them, and presto the counter works!

4th Feb - PLL

Not yet fully understanding how The PLL is tuned, over a range, and exactly how the broadcast capacitor is used I opt for an Echo Falls Chardonnay.

Ran out of wire for L2, dug around and found some spare wire from the K2 construction.

“Lock is achieved, and duely toasted..”

Following the instructions rather to carefully.. PLL fails to lock on any band.. But the VCO band capacitors have yet to be installed! They are installed and for the first time, with the 15m capacitor jumper selected and the varicap tweaked.. Lock is achieved, and duely toasted with a bottle of Martha's Mild

MultiPig PLL
PLL

Lock is then achieved for some of the other bands, when using the jumpered capacitors or with the external broadcast capacitor. But the frequency is 2-3 MHZ to high! Following some more thinking, and a very helpful run through of the circuits operation with a fellow club member. We suspect that one of the divide by lines on the PLL chip is being left permantly high, thus altering the selected frequency. This would also explain why most of the sub bands do not lock with the on board capacitance, or with the large external variable capacitor.

If all the BCD switches are set to 0, in theory all the PLL's divide by pins should now be at 0 volts, as they "should" all be grounded.. Further investigation shows the BCD's are working correctly.. so, something else must be wrong.

Also rechecked the frequency readouts, compared with the BCD settings and they are still a couple or more Mhz apart. Very puzzling..

11th April - Determined to get to the bottom of this. I reread all the documentation.. The PLL can use either a 12Mhz or 10Mhz crystals. Mine has a 12Mhz crystal, but the PLL divide by table in the documentation is for the 10Mhz crystal!

Retested using the broadcast cap and the 12mhz divide by table, which I found on the MultiPig+ site, everything works perfectly.. Brillant!

Read more in MultiPig+ Kit Part Two